Discipline guide

FPGA, RTL & ASIC design and verification internships

Digital hardware engineers describe logic in hardware description languages such as Verilog, SystemVerilog or VHDL, prove it works in simulation, and then implement it on an FPGA or send it to a foundry as a custom chip (ASIC). At chip companies, verification (building testbenches that try to break a design) is often a larger team than design itself.

17 open roles right now: 2 say freshmen or sophomores can apply, 15 don't list a class year. Filter this discipline in the full list.

What interns do

  • Write RTL for a contained block such as a FIFO, arbiter, UART, DMA engine or bus bridge.
  • Build self-checking testbenches in SystemVerilog/UVM or Python (cocotb), run regressions and debug waveforms.
  • Close timing on an FPGA build and explain what changed between a failing and passing run.
  • Script flows in Python or Tcl: parse synthesis, timing and coverage reports into something readable.

Skills to show

  • Digital logic fundamentals: finite-state machines, pipelining, clock-domain crossing, setup and hold.
  • Verilog or SystemVerilog written in a synthesizable style, plus a simulator (Icarus, Verilator, Questa or Xcelium).
  • An FPGA toolchain: Vivado, Quartus, or the open-source Yosys and nextpnr flow.
  • Computer architecture basics (caches, pipelines, RISC-V or ARM instruction sets).
  • Python or Tcl for automation and report parsing.

Starter projects

  1. Implement a UART plus FIFO in Verilog with a self-checking testbench, then run it on an inexpensive FPGA board talking to your laptop.
  2. Build a small pipelined RISC-V (RV32I) core and a cocotb or SystemVerilog test suite; publish which instructions and hazards your tests cover.
  3. Design an asynchronous FIFO with Gray-code pointers for a clock-domain crossing, test it with randomized stimulus, and write up why the synchronizers prevent metastability problems.

Open FPGA/RTL/ASIC roles

Newest first. Labels are automatic; read each posting on the employer's site.

  1. Astranis · San Francisco

    Class year not stated FPGA/RTL/ASIC Analog/mixed-signal Summer 2027 US person / PR ITAR / export

    Why these labels?
    U.S. Citizenship, Lawful Permanent Residency, or Refugee/Asylee Status Required

    Excerpt from the posting (at most 300 characters). Always read the full posting on the employer's site.

  2. Astranis · San Francisco

    Class year not stated FPGA/RTL/ASIC Analog/mixed-signal Winter 2027 US person / PR ITAR / export

    Why these labels?
    U.S. Citizenship, Lawful Permanent Residency, or Refugee/Asylee Status Required

    Excerpt from the posting (at most 300 characters). Always read the full posting on the employer's site.

  3. Astranis · San Francisco

    Class year not stated FPGA/RTL/ASIC Analog/mixed-signal Summer 2027 US person / PR ITAR / export

    Why these labels?
    US Citizenship or Green Card (This is a legal requirement; no exceptions)

    Excerpt from the posting (at most 300 characters). Always read the full posting on the employer's site.

  4. Astranis · San Francisco

    Class year not stated FPGA/RTL/ASIC Analog/mixed-signal Winter 2027 US person / PR ITAR / export

    Why these labels?
    US Citizenship or Green Card (This is a legal requirement; no exceptions)

    Excerpt from the posting (at most 300 characters). Always read the full posting on the employer's site.

  5. Waymo · Mountain View, CA

    Class year not stated FPGA/RTL/ASIC Analog/mixed-signal PCB/hardware Summer 2027

  6. Etched · San Jose

    Class year not stated FPGA/RTL/ASIC Fall 2026 Spring 2027 Summer 2027

  7. Lightmatter · Boston, MA; Mountain View, CA

    Class year not stated FPGA/RTL/ASIC Test/validation Photonics/optics ITAR / export

    Why these labels?
    Export Control

    Excerpt from the posting (at most 300 characters). Always read the full posting on the employer's site.

  8. CesiumAstro · Westminster, CO; Austin, TX · 1 more posting merged

    Class year not stated Co-op FPGA/RTL/ASIC Summer 2027 US person / PR ITAR / export

    Why these labels?
    Please Note: To conform with the United States Government Space Technology Export Regulations, the applicant must be a U.S. citizen, lawful permanent resident of the U.S., conditional resident, asylee or refugee (protected individuals as defined by 8 U.S.C. 1324b(a)(3)), or eligible to obtain the…

    Excerpt from the posting (at most 300 characters). Always read the full posting on the employer's site.

  9. Rocket Lab · Toronto, CAN; Pasadena, CA +1 more · 2 more postings merged

    Class year not stated Embedded/firmware Test/validation FPGA/RTL/ASIC PCB/hardware Summer 2027 US person / PR ITAR / export

    Why these labels?
    To conform to U.S. Government space technology export regulations, including the International Traffic in Arms Regulations (ITAR), Rocket Lab Employees must be a U.S. citizen, lawful U.S. permanent resident (i.e., current Green Card holder), or lawfully admitted into the U.S. as a refugee or…

    Excerpt from the posting (at most 300 characters). Always read the full posting on the employer's site.

  10. SpaceX · Flexible - Any SpaceX Site

    Fr/So friendly Co-op FPGA/RTL/ASIC Spring 2027 US person / PR ITAR / export

    Why these labels?
    Silicon Engineering Intern/Freshman/Sophomore: $30.00/hour Applicant for this intern position must be a (i) U.S. citizen or national, (ii) U.S. lawful permanent resident (e.g., green card holder), (iii) Refugee under 8 U.S.C. § 1157, or (iv) Asylee under 8 U.S.C. § 1158.

    Excerpt from the posting (at most 300 characters). Always read the full posting on the employer's site.

  11. SpaceX · Flexible - Any SpaceX Site

    Fr/So friendly Co-op FPGA/RTL/ASIC Summer 2027 US person / PR ITAR / export

    Why these labels?
    Silicon Engineering Intern/Freshman/Sophomore: $30.00/hour Applicant for this intern position must be a (i) U.S. citizen or national, (ii) U.S. lawful permanent resident (e.g., green card holder), (iii) Refugee under 8 U.S.C. § 1157, or (iv) Asylee under 8 U.S.C. § 1158.

    Excerpt from the posting (at most 300 characters). Always read the full posting on the employer's site.

  12. Astera Labs · Tel Aviv-Yafo, Tel Aviv District, Israel

    Class year not stated FPGA/RTL/ASIC

  13. Etched · San Jose

    Class year not stated FPGA/RTL/ASIC Fall 2026 Spring 2027 Summer 2027

  14. Etched · San Jose

    Class year not stated FPGA/RTL/ASIC Summer 2026 Fall 2026 Spring 2027

  15. Neuralink · South San Francisco, CA

    Class year not stated FPGA/RTL/ASIC Analog/mixed-signal

  16. Etched · San Jose

    Class year not stated FPGA/RTL/ASIC Fall 2026 Spring 2027 Summer 2027

  17. Neuralink · South San Francisco, CA

    Class year not stated FPGA/RTL/ASIC

Other disciplines

Embedded systems & firmware · Analog & mixed-signal · RF, microwave & wireless · Power electronics · PCB & hardware design · Test, validation & reliability · Controls, robotics & GNC · Photonics & optics